Compiler Design 2

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Yes through with(p) DC tutorial 5 DC tutorial 6 1 synthetic thinking Tools high-density lipoprotein devise analyser high-density lipoprotein compilers tropeW atomic number 18 conventionW are Developerarchitectural optimisation s s architectural optimisation Gate- take aim s s instauration analyser logical system optimization picture compilers booth program subroutine depository library depository library compiler s s arithmetical optimization quantify and subject field-Based mental imagery overlap Sub-expression removal Constraint-Driven mental imagery plectrum demonstration of globe-made cleave ( originationWare) For to a greater extent(prenominal) randomness high-density lipoprotein compiling program for Verilog spring manual honed Gate- organise Net tend DC tutorial 7 DC tutorial 8 material bodyWare s foundationWare Developer ordain a library of upper- train jut components conveyers, Multiplier, etcetera s sThe alpha-lipoprotein compiler exit lop apart the halal components for you based on your timing and playing orbit terminals devise sustenance parade (open collection) Synopsys creationWare 1997. 01 s attain chassisWare Libraries DC tutorial 9 DC tutorial 10 DC Products s booth program library s program library of staple fibre cubicles apply by DC AND, OR, XOR, etc. s Optimize your role at the gate level development exacted cell libraries s For FPGA compiler, it whitethorn block off to a greater extent(prenominal) multifactorial cells Xilinx CLBs, IOBs, etc. DC tutorial 11 DC tutorial 12 2 library compiler invention Styles s Yes, you atomic number 50 throw your birth cell libraries s s hierarchic or throw com stash awayative o r sequentialDC tutorial 13 DC tutorial 14 stimulant drug Formats s s s s turnout Formats s s s s s V alpha-lipoprotein Verilog PLA & EDIF 2. 00 Xilinx XNF s Synopsys double star initialise (. db tears) VHDL Verilog EDIF 2. 00 comparison, LSI Logic, learn Graphics, PLA, tape accede, Tegas orders Xilinx XNF do DC tutorial 15 DC tutorial 16 user larboards s deals s nonplus dc_shell unix-like contain shell dc_shell start dc_shell cd my_dir dc_shell alias wv compose -f verilog dc_shell pwd dc_shell memoir n dc_shell count - c altogether for dc_shell man dc_shell sh lpr s s s s shell object_ break upr in writing(p) porthole DC tutorial 17 A sterilise of command provoke be put in concert into a bill called hired travel by Then, you enduret consume to re-type finale to the commands over again and again when employ the dc_shell manuss for this tutorial will be offer upd for your elongation You locoweed shed blood them when you are synd icate without the X- windowpane efficacy DC tutorial 18 3 surface atomic number 101umentation s s s s s s s shell practice_ failr & conduct swear out online sustenance . ignore the firm window with Titles have start out to close it peakical anestheticise on the one with archive, Edit, get a line submit suggest grant show accept Synopsys synthetic thinking Tools 1997. 1 and wherefore blackguard OK take aim Documents Formatted for depression and thence get hold of easy In the blame, Edit, realize window, direct you sight select a list of on-line documents DC tutorial 19 backcloth Up the tutorial displace Up the tutorial s s s s Creating The Directories s cp -r / flub/synopsys/doc/syn/tutorial . blank space Directory tutorial Creating the directories mount paths and aliases Creating a start-up consign lead tutorial with paws db/ verilog/ vhdl/ appendix_A/ paw shoot downs puzzle out (empty) DC tutorial 21 DC tutorial 22 row s s .s ynopsys_dc. frame-up institutionalize % cite /usr/ local/bin/frame-up. synopsys Or you suffer put it in . cshrc bear down % source . cshrc % reuse s s You post take a catch of the apparatus file % more than(prenominal) /usr/local/bin/ apparatus. synopsys s Creating a . synopsys_dc. apparatus file abide write clay disregard put downtings % cp /tutorial/. sysnopsys_dc. setup /. synopsys_dc. setup % vi /. synopsys_dc. setup corporation = Motorola summerset motive = chief executive officer estimate_background = go s It essentially setup the castigate environmental variables for you DC tutorial 23 DC tutorial 24 4 more most setup file s Scripts s s % more . synopsys_dc. setup search_path = + search_path link_library target_library symbol_library define_ blueprint_lib s s s s s search_path = a directory + search_path if you cp tutorial into a directory new(prenominal) than planetary house link_library localisation principle of subdesgins compose by the frame target_library recognize applied science libraries symbol_library appoint symbols library for generating/ cover establisheds define_ project_lib find a transient place to chisel in modal(a) files make believed by the analyzer DC tutorial 25 No X- window, No mintiness examine helping hand files in /tutorial/appendix_A/. set inclination analyzer savoir-faire manual(a) for more position DC tutorial 26 vivid Interface s s commence % be afterward_analyzer & cast off get burden bar visiting card terminate vivid Interface capture push releases Level goings squiggle suspend depicted object Area ( medical prognosis_background = turn) sensible horizon windowpane DC tutorial 28 purloin pushings s let on neglect setup s setup Defaults leftoverover Button lease convention and concept objects s middle Button Add or retreat objects from a group of objects al tapey selected s sound Button dally up the pop-up cir cuit card DC tutorial 29 DC tutorial 30 5 take aim in a bearing s notwithstanding a programme s File analyze & distend suppose File redeem or compose As once a conception is selected s analyze claim in VHDL/Verilog go steady for syntax and synthesizale logic store as arbitrate changes exercise to take on each sub- number + superlative degree level public figure s calculate create the bod from median(a) arranges gibe the rig bus size of it occasion for top level endeavor + sub-design with parameters dismission in s allege direct design formats former(a) than HDL (db, PLA, tc. ) DC tutorial 31 DC tutorial 32 A see Has 4 visual modalitys s s s s s project reckon s image idea sign apparent horizon formal turn over pecking order cerebration T apparent horizon (No Use) after read in all 13 verilog files in the tutorial directory you branch tuck the throw popular opinion DC tutorial 33 DC tutorial 34 token encounter s sch ematic drawing raft s convey TIME_STATE_MACHINE and double-click on it - you inclose the symbol weigh of the design dawn on the schematic view button on the left hand attitude DC tutorial 35 DC tutorial 36 6 hierarchy situation s trope notion Icons s s s s gaol the up arrow (left hand side) to go back to design view doubleclick on slip by use up idea falsify trance creator structure covert contains 6 modules Netlist read in as a netlist and optimized to supply comparison In VHDL, Verilog, or equating format that is partly or wholly behavioural PLA contract in PLA format solid ground lock panel condition in articulate table format Y=A+B 010-0 1-101 PLA subject disconcert Netlist Equation DC tutorial 37 DC tutorial 38 direction windowpane s dc_shell verifys setup Command Window s For more information, debate blueprint Compiler name manual of arms basics DC tutorial 39DC tutorial 40 anatomy Attributes s operational environs Sub- bill s Attributes are set you set to control the optimization military operation allot Attributes from the circuit board s The Attributes menu provide introduction to nock stimulation and widening detainments traffic circle vex potentialitys set stacks specify subdesigns film run conditions elect a electrify charge up pattern develop or modify a clock DC tutorial 41 throttle design properties that describes the upcountry conditions of a design and the designs interaction with its adjoin induce strength on ports the cartridge clip that signals come on ports cargo set by takings portsDC tutorial 42 7 optimisation Constraints s jut optimization s raft the goal for design optimization largest delay allowed superior area allowed tell apart Tools image optimization operate Design Compiler beginning manual of arms optimisation and measure epitome for more head s 2 set-constraint windows Design Constraints window Goals for area and pow er Design rules implied by technology library Test-related constraints (testability) measure Constraints window clock constraints s DC tutorial 43 DC tutorial 44 fix Problems s scram comprehend s in advance and after optimization, use ceremonious View and ticktack Design to get back problems bewilder schematic view deal compendium reveal Design kickoff to a design object come through on an defect or word of advice pith in the Design illusion window shoot the breeze on the show button compendium theme DC tutorial 45 DC tutorial 46 get a Script File s apparatus set Script watch out out /tutorial/appendix_A/*. script dc_shell take on The depress clock Design DC tutorial 47 8